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RT8020E 1 ds8020e-02 march 2011 www.richtek.com applications z digital still cameras z mobile phones z personal information appliances z wireless and dsl modems z mp3 players z portable instruments note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. ordering information pin configurations (top view) wdfn-12l 3x3 dual high-efficiency pwm step-down dc/dc converter features z z z z z 2.5v to 5.5v input range z z z z z 1.2v and 1.8v fixed output voltage z z z z z 1a output current z z z z z 95% efficiency z z z z z no schottky diode required z z z z z 50 a quiescent current per channel z z z z z 1.5mhz fixed frequency pwm operation z z z z z small 12-lead wdfn package z z z z z rohs compliant and halogen free marking information general description the RT8020E is a dual high-efficiency pulse-width- modulated (pwm) step-down dc/dc converter. it is capable of delivering 1a output current over a wide input voltage range from 2.5v to 5.5v. the RT8020E is ideally suited for portable electronic devices that are powered by 1-cell li-ion battery or other power sources within the range such as cellular phones, pdas and other hand-held devices. two operational modes are available : pwm/low-dropout auto-switch mode and shutdown mode. internal synchronous rectifier with low r ds(on) dramatically reduces conduction loss at pwm mode. no external schottky diode is required in practical application. the RT8020E enters low-dropout mode when normal pwm cannot provide regulated output voltage by continuously turning on the upper pmos. the RT8020E enters shutdown mode and consumes less than 0.1 a when the en pin is pulled low. the switching ripple is easily smoothed-out by small package filtering elements due to a fixed operation frequency of 1.5mhz. this, along with a small wdfn-12l 3x3 package, provides an ideal solution for small pcb area application. other features include soft start, lower internal reference voltage with 2% accuracy, over temperature protection, and over current protection. vin2 lx2 nc1 fb1 en2 nc2 fb2 lx1 gnd gnd en1 vin1 11 10 9 1 2 3 4 5 12 67 8 gnd 13 js=ym dnn js= : product code ymdnn : date code RT8020E package type qw : wdfn-12l 3x3 (w-type) lead plating system p : pb free g : green (halogen free and pb free) fixed output voltage : vout1/vout2 1.2v/1.8v
RT8020E 2 ds8020e-02 march 2011 www.richtek.com typical application circuit functional pin description pin no. pin name pin function 1 vin2 power input of channel 2. 2 lx2 pin for switching of channel 2. 3, 9, 13 (exposed pad) gnd ground. the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation. 4 fb1 feedback of channel 1. 5, 11 nc1, nc2 no internal connection or connect to v in . 6 en1 chip enable of channel 1 (active high). v en1 Q v in1. 7 vin1 power input of channel 1. 8 lx1 pin for switching of channel 1. 10 fb2 feedback of channel 2. 12 en2 chip enable of channel 2 (active high). v en2 Q v in2. en2 nc2 fb2 vin2 lx2 fb1 RT8020E 1 2 4 9 10 11 gnd lx1 gnd 8 5 nc1 12 v out2 l2 4.7h c in2 10f vin1 7 6 en1 v in1 4.7f l1 4.7h 4.7f v out1 10f v in2 c out1 c in1 c out2 3, 13 (exposed pad) 1.8v 1.2v
RT8020E 3 ds8020e-02 march 2011 www.richtek.com function block diagram driver control logic current limit detector osc and shutdown control current sense v ref fbx gnd lxx pwm comparator slope compensation error amplifier uvlo and power good detector rc comp enx vinx r s1 r s2
RT8020E 4 ds8020e-02 march 2011 www.richtek.com absolute maximum ratings (note 1) z supply input voltage, v in1 , v in2 ----------------------------------------------------------------------------------- ? 0.3v to 6.5v z en1, fb1, lx1, en2, fb2 a nd lx2 pin voltage --------------------------------------------------------------- ? 0.3v to v in + 0.3v z power dissipation, p d @ t a = 25 c wdfn-12l 3x3 --------------------------------------------------------------------------------------------------------- 1.667w z package thermal resistance (note 2) wdfn-12l 3x3, ja --------------------------------------------------------------------------------------------------- 60 c/w wdfn-12l 3x3, jc --------------------------------------------------------------------------------------------------- 8.2 c/w z lead temperature (soldering, 10 se c.) --------------------------------------------------------------------------- 260 c z junction temperature ------------------------------------------------------------------------------------------------- 150 c z storage temperature range ---------------------------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body mode) ------------------------------------------------------------------------------------------ 2kv mm (ma chine mode) -------------------------------------------------------------------------------------------------- 200v electrical characteristics parameter symbol test conditions min typ max unit channel 1 and channel 2 under voltage lock out threshold v uvlo -- 1.8 -- v hysteresis -- 0.1 -- v quiescent current i q i out = 0ma, v fb = v ref + 5% -- 50 70 a shutdown current i shdn en = gnd -- 0.1 1 a v out1 v in1 = 2.5v to 5.5v, v out1 = 1.2v 0a < i out1 < 1a ? 2 -- 2 % output voltage accuracy v out2 v in2 = 2.5 to 5.5v, v out2 = 1.8v 0a < i out2 < 1a ? 2 -- 2 % fb input current i fb v fb = v in ? 50 -- 50 na v in = 2.5v -- 0.38 -- r ds (on) of p-mosfet r ds(on)_p i out = 200ma v in = 3.6v -- 0.28 -- v in = 2.5v -- 0.35 -- r ds (on) of n-mosfet r ds(on)_n i out = 200ma v in = 3.6v -- 0.25 -- p-channel current limit i li m_p v in = 2.5v to 5.5 v 1.4 1.5 2 a logic-high v ih v in = 2.5v to 5.5v 1.5 -- v in en input threshold voltage logic-low v il v in = 2.5v to 5.5v -- -- 0.4 v oscillator frequency f osc v in = 3.6v, i out = 100ma 1.2 1.5 1.8 mhz to be continued recommended operating conditions (note 4) z supply input voltage, v in1 , v in2 ----------------------------------------------------------------------------------- 2.5v to 5.5v z junction temperature range ---------------------------------------------------------------------------------------- ? 40 c to 125 c z ambient temperature range ---------------------------------------------------------------------------------------- ? 40 c to 85 c (v in = 3.6v, v out = 1.8v, l = 4.7 h, c in = 4.7 f, c out = 10 f, i max = 1a, t a = 25c, unless otherwise specified)
RT8020E 5 ds8020e-02 march 2011 www.richtek.com parameter symbol test conditions min typ max unit thermal shutdown temperature t sd -- 160 -- c maximum duty cycle d max 100 -- -- % lx leakage current i lx v in = 3.6v, v lx = 0v or v lx = 3.6v ? 1 -- 1 a note 1. stresses listed as the above ? absolute maximum ratings ? may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. ja is measured in natural convection at t a = 25 c on a high effective thermal conductivity four-layer test board of jedec 51-7 thermal measurement standard. the measurement case position of jc is on the exposed pad of the package. note 3. devices are esd sensitive. handling precaution recommended. note 4. the device is not guaranteed to function outside its operating conditions.
RT8020E 6 ds8020e-02 march 2011 www.richtek.com typical operating characteristics ch2 output voltage vs. input voltage 1.78 1.79 1.80 1.81 1.82 1.83 2.5 3.0 3.5 4.0 4.5 5.0 input voltage (v) output voltage (v) v out = 1.8v, l = 4.7 h, c out = 10 f i out = 0ma i out = 300ma i out = 600ma ch2 output voltage vs. output current 1.76 1.78 1.80 1.82 1.84 1.86 0 0.2 0.4 0.6 0.8 1 output current (a) output voltage (v) v in = 3v v in = 3.6v v in = 4.2v v in = 5v v out = 1.8v, l = 4.7 h, c out = 10 f ch1 efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 0 0.2 0.4 0.6 0.8 1 output current (a) efficiency (%) v out = 1.2v, l = 4.7 h, c out = 10 f v in = 2.4v v in = 2.7v v in = 3v v in = 3.3v v in = 3.6v v in = 3.9v v in = 4.2v v in = 4.5v ch1 output voltage vs. input voltage 1.18 1.19 1.20 1.21 1.22 1.23 2.5 3.0 3.5 4.0 4.5 5.0 input voltage (v) output voltage (v) v out = 1.2v, l = 4.7 h, c out = 10 f i out = 0ma i out = 300ma i out = 600ma ch1 output voltage vs. output current 1.18 1.19 1.20 1.21 1.22 1.23 0 0.2 0.4 0.6 0.8 1 output current (a) output voltage (v) v out = 1.2v, l = 4.7 h, c out = 10 f v in = 3v v in = 3.6v v in = 4.2v v in = 5v ch2 efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 0 0.2 0.4 0.6 0.8 1 output current (a) efficiency (%) v in = 2.4v v in = 2.7v v in = 3v v in = 3.3v v in = 3.6v v in = 3.9v v in = 4.2v v in = 4.5v v out = 1.8v, l = 4.7 h, c out = 10 f
RT8020E 7 ds8020e-02 march 2011 www.richtek.com switching frequency vs. temperature 1300 1350 1400 1450 1500 1550 1600 -50 -25 0 25 50 75 100 125 temperature (c) switching frequency (khz) 1 v in = 3.7v, v out = 1.8v, l = 4.7 h, c out = 10 f, i out = 300ma switching frequency vs. input voltage 1300 1350 1400 1450 1500 1550 1600 2.5 3 3.5 4 4.5 5 input voltage (v) switching frequency (khz) 1 v out = 1.8v, l = 4.7 h, c out = 10 f, i out = 300ma en pin threshold vs. input voltage 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 input voltage (v) en pin threshold (v ) rising falling v out = 1.2v, l = 4.7 h, c out = 10 f, i out = 0a en pin threshold vs. temperature 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 -50 -25 0 25 50 75 100 125 temperature (c) en pin threshold (v ) rising falling v out = 1.2v, l = 4.7 h, c out = 10 f, i out = 0a ch2 output voltage vs. temperature 1.74 1.75 1.76 1.77 1.78 1.79 1.80 1.81 1.82 1.83 -50 -25 0 25 50 75 100 125 temperature (c) output voltage (v) v in = 2.5v v in = 3.7v v in = 4.5v v out = 1.8v, l = 4.7 h, c out = 10 f, i out = 300ma ch1 output voltage vs. temperature 1.14 1.15 1.16 1.17 1.18 1.19 1.20 1.21 1.22 -50 -25 0 25 50 75 100 125 temperature (c) output voltage (v) v in = 2.5v v in = 3.7v v in = 4.5v v out = 1.2v, l = 4.7 h, c out = 10 f, i out = 300ma
RT8020E 8 ds8020e-02 march 2011 www.richtek.com output current limit vs. temperature 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 -50 -25 0 25 50 75 100 125 temperature (c) output current limit (a ) v in = 3.6v v in = 5v v in = 2.5v v out = 1.2v, l = 4.7 h, c out = 10 f output current limit vs. input voltage 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.5 3.0 3.5 4.0 4.5 5.0 input voltage (v) output current limit (a ) v out = 1.2v, l = 4.7 h, c out = 10 f ch1 power on from en v en (2v/div) time (500 s/div) v out (1v/div) v in = 3.6v, v out = 1.2v, i out = 1a i in (1a/div) ch1 power on from en v en (2v/div) time (100 s/div) v out (1v/div) i in (500ma/div) v in = 3.6v, v out = 1.2v, i out = 10ma ch1 power off from en v en (2v/div) time (500 s/div) v out (1v/div) v in = 3.6v, v out = 1.2v, i out = 1a i in (1a/div) ch1 power off from en v en (2v/div) time (100 s/div) v out (1v/div) i in (500ma/div) v in = 3.6v, v out = 1.2v, i out = 10ma
RT8020E 9 ds8020e-02 march 2011 www.richtek.com power off from v in time (1ms/div) v in = 3.6v, v out = 1.2v, i out = 10ma v in (2v/div) v out (1v/div) i in (500ma/div) power on from v in time (250 s/div) v in = 3.6v, v out = 1.2v, i out = 10ma v in (2v/div) v out (1v/div) i in (500ma/div) ch2 power off from en v en (2v/div) time (500 s/div) v out (1v/div) i in (1a/div) v in = 3.6v, v out = 1.8v, i out = 1a ch2 power on from en v en (2v/div) time (500 s/div) v out (1v/div) i in (1a/div) v in = 3.6v, v out = 1.8v, i out = 1a ch2 power on from en v en (2v/div) time (100 s/div) v out (1v/div) i in (500ma/div) v in = 3.6v, v out = 1.8v, i out = 10ma ch2 power off from en time (100 s/div) v en (2v/div) v out (1v/div) i in (500ma/div) v in = 3.6v, v out = 1.8v, i out = 10ma
RT8020E 10 ds8020e-02 march 2011 www.richtek.com load transient response time (1ms/div) v in = 3.6v, v out = 1.2v, i out = 50ma to 1a v out (20mv/div) i out (500ma/div) load transient response time (1ms/div) v in = 3.6v, v out = 1.2v, i out = 50ma to 500ma v out (20mv/div) i out (500ma/div) output voltage ripple v lx (2v/div) time (500ns/div) v out (5mv/div) v in = 3.6v, v out = 1.2v, i out = 1a output voltage ripple time (500ns/div) v in = 5v, v out = 1.2v, i out = 1a v lx (2v/div) v out (5mv/div) load transient response time (1ms/div) v in = 5v, v out = 1.2v, i out = 50ma to 1a v out (20mv/div) i out (500ma/div) load transient response time (1ms/div) v in = 5v, v out = 1.2v, i out = 50ma to 500ma v out (20mv/div) i out (500ma/div)
RT8020E 11 ds8020e-02 march 2011 www.richtek.com applications information the basic RT8020E application circuit is shown in typical application circuit. external component selection is determined by the maximum load current and begins with the selection of the inductor value and operating frequency followed by c in and c out . inductor selection for a given input and output voltage, the inductor value and operating frequency determine the ripple current. the ripple current i l increases with higher v in and decreases with higher inductance. having a lower ripple current reduces the esr losses in the output capacitors and the output voltage ripple. highest efficiency operation is achieved at low frequency with small ripple current. this, however, requires a large inductor. a reasonable starting point for selecting the ripple current is i l = 0.4(i max ). the largest ripple current occurs at the highest v in . to guarantee that the ripple current stays below a specified maximum, the inductor value should be chosen according to the following equation : inductor core selection once the value for l is known, the type of inductor can be selected. high efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, thus, limiting the use to more expensive ferrite or permalloy cores. actual core loss is independent of core size for a fixed inductor value, but it is very dependent on the inductanc e selected. as the inductance increases, core losses decrease. however, increas ed inductance requires more turns of wire and therefore higher copper losses. ferrite designs have very low core losses and are preferred at high switching frequencies, thus allowing design goals to concentrate on copper loss and saturation prevention. ferrite core material saturates ? hard ? , which means that inductance collapses abruptly when the peak design current is exceeded. this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is commonly used for design because even significant deviations do not result in much difference. note that ripple current ratings from capacitor manufacturers are often based on a life time of only 2000 hours, which makes it advisable to further de-rate the capacitor or choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet the size or height requirements in the design. the selection of c out is determined by the effective series resistance (esr) that is required to minimize voltage ripple and load step transients, as well as by the amount of bulk capacitance that is necessary to ensure that the control loop is stable. loop stability can be checked by viewing the load transient response as described in a later section. the output ripple, v out , is determined by : ? ? ? ? ? ? ? ? ? ? ? ? ? = in out out l v v 1 l f v i ? ? ? ? ? ? ? ? ? ? ? ? ? = in(max) out l(max) out v v 1 i f v l ? ? ? ? ? ? + out l out 8fc 1 esr i v 1 v v v v i i out in in out out(max) rms ? = this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! different core materials and shapes will change the size/ current and price/current relationship of an inductor. toroid or shielded pot cores in ferrite or permalloy materials are small and don't radiate energy but generally cost more than powdered iron core inductors with similar characteristics. the choice of which type of inductor to use mainly depends on the price vs. size requirements and any radiated field/emi requirements. c in and c out selection the input capacitance, c in , is needed to filter the trapezoidal current at the source of the top mosfet. to prevent large ripple voltage, a low esr input capacitor sized for the maximum rms current should be used. rms current is given by :
RT8020E 12 ds8020e-02 march 2011 www.richtek.com the output ripple is highest at maximum input voltage since i l increases with input voltage. multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirements. dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. special polymer capacitors offer very low esr, but have lower capacitance density than other types. tantalum capacitors have the highest capacitance density, but it is important to only use types that have been surge tested for use in switching power supplies. aluminum electrolytic capacitors have significantly higher esr, but can be used in cost-sensitive applications provided that consideration is given to ripple current ratings and long-term reliability. ceramic capacitors have excellent low esr characteristics, but can have a high voltage coefficient and audible piezoelectric effects. the high q of ceramic capacitors with trace inductance can also lead to significant ringing. using ceramic input and output capacitors higher value, lower cost ceramic capacitors are now becoming available in smaller case sizes. their high ripple current, high voltage rating and low esr make them ideal for switching regulator applications. however, care must be taken when these capacitors are used at the input and output. when a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, v in . at best, this ringing can couple to the output and be mistaken as loop instability. at worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at v in large enough to damage the part. efficiency considerations the efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. efficiency can be expressed as : efficiency = 100% ? (l1+ l2+ l3+...) where l1, l2, etc. are the individual losses as a percentage of input power. although all dissipative elements in the circuit produce losses, two main sources usually account for most of the losses : v in quiescent current and i 2 r losses. the v in quiescent current loss dominates the efficiency loss at very low load currents whereas the i 2 r loss dominates the efficiency loss at medium to high load currents. in a typical efficiency plot, the efficiency curve at very low load currents can be misleading since the actual power lost is of no consequence. 1.the v in quiescent current appears due to two components : the dc bias current and the gate charge currents. the gate charge current results from switching the gate capacitance of the internal power mosfet switches. each time the gate is switched from high to low to high again, a packet of charge q moves from v in to ground. the resulting q/ t is the current out of v in that is typically larger than the dc bias current. in continuous mode, i gatechg = f(q t + q b ) where q t and q b are the gate charges of the internal top and bottom switches. both the dc bias and gate charge losses are proportional to v in and thus their effects will be more pronounced at higher supply voltages. 2. i 2 r losses are calculated from the resistances of the internal switches, r sw and external inductor, r l . in continuous mode the average output current flowing through inductor l is ? chopped ? between the main switch and the synchronous switch. thus, the series resistance looking into the lx pin is a function of both top and bottom mosfet r ds(on) as well as the duty cycle (d c). the equation is shown below : r sw = r ds(on)top x dc + r ds(on)bot x (1 ? dc) the r ds(on) for both the top and bottom mosfets can be obtained from the typical performance characteristics curves. thus, to obtain i 2 r losses, simply add r sw to r l and multiply the result by the square of the average output current. other losses including c in and c out esr dissipative losses and inductor core losses generally account for less than 2% of the total loss. checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take
RT8020E 13 ds8020e-02 march 2011 www.richtek.com layout considerations follow the pcb layout guidelines for optimal performance of the RT8020E. ` for the main current paths, keep their traces short and wide. ` place the input capacitor as close as possible to the device pins (vin and gnd). ` lx node experiences high frequency voltage swing and should be kept in a small area. keep analog components away from lx node to prevent stray capacitive noise pick-up. ` connect feedback network behind the output capacitors. keep the loop area small. place the feedback components near the RT8020E. ` connect all analog grounds to a command node and then connect the command node to the power ground behind the output capacitors. figure 1. derating curve for RT8020E package 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w) several cycles to respond to a step in load current. when a load step occurs, v out immediately shifts by an amount equal to i load (esr), where esr is the effective series resistance of c out . i load also begins to charge or discharge c out, generating a feedback error signal used by the regulator to return v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing which would indicate a stability problem. thermal considerations the maximum power dissipation depends on the thermal resistance of ic package, pcb layout, rate of surrounding airflow, and difference between junction and ambient temperature. the maximum power dissipation can be calculated by the following formula : p d(max) = ( t j(max) ? t a ) / ja where t j(max) is the maximum junction temperature, t a is the ambient temperature and ja is the junction to ambient thermal resistance. for recommended operating conditions specification of the RT8020E dc/dc converter, t j(max) is the maximum junction temperature of the die and t a is the ambient temperature. the junction to ambient thermal resistance ja is layout dependent. for wdfn- 12l 3x3 packages, the thermal resistance, ja , is 60 c/ w on a standard jedec 51-7 four-layer thermal test board. the maximum power dissipation at t a = 25 c can be calculated by the following formula : p d(max) = (125 c ? 25 c) / (60 c/w) = 1.667w for wdfn-12l 3x3 package the maximum power dissipation depends on the operating ambient temperature for fixed t j(max) and thermal resistance, ja . for the RT8020E package, the derating curves in figure 1 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation.
RT8020E 14 ds8020e-02 march 2011 www.richtek.com richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 information that is provided by richtek technology corporation is believed to be accurate and reliable. richtek reserves the ri ght to make any change in circuit design, specification or other related things if necessary without notice at any time. no third party intellectual property inf ringement of the applications should be guaranteed by users when integrating richtek products into any application. no legal responsibility for any said applications i s assumed by richtek. richtek technology corporation taipei office (marketing) 5f, no. 95, minchiuan road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)86672399 fax: (8862)86672377 email: marketing@richtek.com w-type 12l dfn 3x3 package outline dimension dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.150 0.250 0.006 0.010 d 2.950 3.050 0.116 0.120 d2 2.300 2.650 0.091 0.104 e 2.950 3.050 0.116 0.120 e2 1.400 1.750 0.055 0.069 e 0.450 0.018 l 0.350 0.450 0.014 0.018 1 1 2 2 note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options

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